1. Field of the Invention
This invention relates to a semiconductor IC device and more particularly to an improvement in which transmission delay time due to a parasitic capacitance is minimized in a TTL-IC device.
2. Description of the Prior Art
FIG. 1 is a diagram of an inverter circuit, such as shown in "Advanced Schottky Family" with a subtitle "ALS and AS Applications" of Application Report published in 1984 by Texas Instruments. FIGS. 2A and 2B respectively show a plan view and a corresponding sectional view in the vicinity of an input transistor in such an inverter, which is adopted in M74ALS1034P (Lot No. 5270P1) of Mitsubishi.
Referring to these FIGS. 1, 2A and 2B in which the same reference characters are used for corresponding portions, an input PNP transistor 1 is formed in an element region 8 of an N type isolated by an isolation layer 16 on a semiconductor substrate 15 of a P type. With this PNP transistor 1, a base region 1a in an N epitaxial layer 20 is connected through an N buried layer 14 and an N.sup.+ diffused layer 13 to an input terminal 3 by a metal lead 2; a collector region 1b is connected to a grounding terminal 4 by a metal lead 17; and an emitter region 1c is connected through a resistor 5 to a power terminal 6 by a metal lead 18. A schottky barrier diode (SBD) 7 is also formed in the same element region 8. A cathode of this SBD 7 is connected by the metal lead 2 to the input terminal 3 through the base region 1a of the input PNP transistor 1, while an anode of the SBD 7 is connected by a metal lead 10 to an emitter of a first NPN transistor 11 and a base of a second NPN transistor 9. In FIG. 1, there are further provided a third NPN transistor 21 and a resistor 12, while the metal lead 10 causes a parasitic capacitance 19.
When a logic "L" of a low voltage is applied to the input terminal 3 in the above structured circuit, the PNP transistor 1 is turned on and causes a "L" current therethrough; as a result, each of the NPN transistors 11, 9, 21 is turned off. At this time, the SBD 7 is supplied with a forward voltage, and then electric charge accumulated in the base region of the second NPN transistor 9 and the parasitic capacitance 19 is discharged. This makes it easy to turn off the second NPN transistor 9.
On the other hand, when a logic "H" of a high voltage is applied to the input terminal 3, the PNP transistor 1 is turned off. Accordingly, the NPN transistors 11, 9, and 21 are turned on in order. At this time, it is necessary to charge the parasitic capacitance 19 up to 2V.sub.BE (V.sub.BE : base-emitter voltage) so that the second NPN transistor may be turned on.
It will be understood from the following equation that time T necessary for charging up the parasitic capacitance 19 depends directly on total area S of the metal lead 10. ##EQU1##
C.sub.o : capacity per unit area of the metal lead 10,
I: emitter current of the first NPN transistor 11,
V.sub.IL : input "L" voltage,
V.sub.F : forward voltage of the SBD 7
When the first and second NPN transistor 11, 9 are formed far away from the input PNP transistor 1 for a certain reason, the metal lead 10 becomes long because the SBD 7 and the input PNP transistor 1 in the above conventional IC device are always formed in the same element region 8. This results in increase of total area S of the metal lead 10. Therefore, when the input signal changes from "L" to "H", longer time is required for charging up the parasitic capacitance 19. This means increase of the transmission delay time.